A dynamic random access memory (DRAM) is capable of storing information based on the amount of charge held in a storage capacitor for each memory cell in the array. Over time, the charge in the storage capacitor dissipates and must be restored to maintain the integrity of the data held in memory. Accordingly, a number of prior art schemes have been proposed to “refresh” the data held in a memory. One approach for implementing memory refresh incorporates an automatic process controlled by a timer to define the interval required for refresh. As the density of memory arrays has expanded, the charging and discharging of the storage capacitors in each cell of the memory begins to represent a significant source of power dissipation. Accordingly, if power can be reduced on a unit cell basis, then a significant power savings can be realized for an entire array.